Conventional fabrication of an integrated circuit device involves placing numerous device structures, such as MOFSETs, bipolar transistors, and doped contact regions, on a single monolithic substrate. The device structures are then electrically interconnected with conductive lines or structures so as to implement desired circuit function. The interconnection of the device structures may be done over several stacked levels.
In order to produce ever faster and smaller integrated circuit devices, the integrated circuit industry has continuously increased the density of the device structures on the substrate surface. The increasingly higher device structure density has resulted in a continuous reduction in the separation between conductive structures and layers of materials, a reduction of the width and thickness of conductive lines and an increase the total length of the conductive lines. This has further resulted in a number of adverse effects. For example, by reducing the spacing between conductive materials in the integrated circuit device, an increase in a phenomenon known as parasitic capacitance or capacitive crosstalk is observed, wherein a change in voltage on one conductive structure effect the voltage on nearby conductive structures. The capacitance between two conductive structures can be expressed as C=k.di-elect cons..sub.o A/d, where k is the relative permitivity or the dielectric constant of the material between the two metal structures, .di-elect cons..sub.o =8.85.times.10.sup.-12 F/m is the absolute permitivity, A is the area of the metal structures, and d is the distance between the metal structures. As the conductive structures of an integrated circuit are packed more closely together, the parasitic capacitance between the conductive structures increases. Also, the electrical resistance increases due to the increase of the total length but the reduction of the cross section area of the conductive lines. The increasing capacitance and resistance degrades the speed and performance of the integrated circuit device. This phenomenon is often referred to as RC delay in the integrated circuit industry.
RC delay can be expressed by the unit of time. (Reference, S. M. Sze, VLSI Technology. McGraw-Hill Book Company, 1988.) RC=R.sub.s L.sup.2.di-elect cons./d, where R.sub.s is the sheet resistance of the conductive lines, L is the length of the conductive line, .di-elect cons.=k.di-elect cons..sub.o is the permitivity of the dielectric materials between conductive lines, and d is the separating spacing between conductive lines. As can be seen in the equation, when the feature density increases, L becomes longer, and d becomes smaller. This results in increased RC delay. In the early stage of integrated circuit industry, increased density caused a negligible increase in RC delay. However, as the integrated circuit industry moves toward sub-micron technology, the scale of RC delay has become significant. Simply increasing the feature density of the device cannot increase the device speed much.
Two approaches to resolving the RC delay include: (1) using materials with increasingly lower dielectric constant as insulation between conductive structures to reduce the permitivity .di-elect cons.=k.di-elect cons..sub.o, and (2) fabricating the metals forming the conductive structures from materials with increasingly lower resistance to reduce the sheet resistance R.sub.s. The use of metals, such as copper, having a lower electrical resistance than the widely used aluminum and aluminum-copper alloys are currently under consideration and development. However, the use of lower resistance metals will not completely resolve the RC delay phenomenon, particularly the parasitic capacitance problem, as the conductive structures become inevitably more closely packed.
Using lower dielectric constant materials is more effect than using better conductive materials alone. For example, sheet resistance is directly related to the electrical resistivity of the conductive material used. The resistivity of aluminum, which is conventionally used as the conductive material for integrated circuit device, is 2.8.times.10.sup.-8 ohm.multidot.m. The resistivity of copper is 1.7.times.10.sup.-8 ohm.multidot.m. Therefore, by replacing the aluminum with copper, the RC delay can be reduced by (2.8-1.7)*100%/2.8=39%. Even if aluminum is replaced by the best conductive material, silver, which has the resistivity of 1.6.times.10.sup.-8 ohm.multidot.m, the RC delay can be reduced by only 43%. On the other hand, the relative permitivity of SiO.sub.2, the currently widely used dielectric material, is about 4. The physical minimum relative permitivity is 1. Therefore, theoretically, the RC delay can be reduced by (4-1)*100%/4=75% by using a vacuum gap. If a dielectric material with a relative permitivity value of 2 is used, the RC delay is reduced by 50%, which is still better than the approach of reducing sheet resistance. However, it is preferred to use a combination of both dielectrics with low permitivity and conductors with low resistivity.
Accordingly, the use of dielectric materials having a lower dielectric value than the widely used SiO.sub.2 and doped silicon oxides are currently under consideration and development. Current dielectric materials have a k value approximately between 3.9 and 4.3. New low-k dielectric materials under consideration, such as TEFLON and organic dielectrics, may be able to achieve k values as low as 2. However, the use of many kinds of low-k dielectric materials is not feasible due to the fact that the chemical and physical properties of many low-k dielectric materials are difficult to make compatible with, or integrate into, the conventional integrated circuit fabricating processes.
The minimum theoretical dielectric constant value is 1.0 for a total vacuum. However, it is well known that air has a dielectric constant of 1.0005, which approaches the minimum theoretically physically possible value of dielectric constant. A number of approaches have been suggested for using air pockets formed within an integrated circuit device between closely spaced conductive structures both on the same level and between on different levels. However, previous efforts have suffered from a number of problems including, but not limited to, (1) process steps that are incompatible with the industry preferred processes such as damascene processes when copper will be used as conductive materials, (2) lack of sufficient control of the size and location of the air pockets, (3) the formation of open voids, (4) formation of gas pockets too close to conductive structures that are liable to filling by conductive material, (5) integrated circuit devices that are mechanically fragile or brittle, (6) the inability to stack multiple layers due to the fragility of underlying layers, (7) a significantly reduced ability of integrated circuit device to dissipate heat, and (8) direct exposure of the conductive structures to air which may result in undesirable chemical changes in the nature of conductive structures.
In order to reduce the RC delay for the conductive features or structures with small separation spacing, a new dielectric isolation scheme is required. What is needed is a process for forming air pockets to provide dielectric isolation in integrated circuit devices that avoids the difficulties encountered in prior efforts. In particular, what is needed is a process that is compatible with preferred fabrication processes for making integrated circuit devices, including but not limited to, various damascene processes, and which will not generally result in (a) the formation of open voids, (b) the formation of air pockets that are vulnerable to being filled with metallic materials in subsequent processes steps, (c) a significant decrease in the mechanical strength of the integrated circuit devices, or (d) a significant reduction in the heat dissipation capacity of the device.